May 2020

32 POWER CONVERTERS www.analog.com Issue 2 2020 Power Electronics Europe www.power-mag.com applications in which decoupling with a bypass capacitor is only possible on the bottom side of the board. One example is when there is not enough space for a large decoupling capacitor. In such cases, vias are used to connect the capacitor. Unfortunately, they have a few nanohenries of parasitic inductance. To keep this connection impedance as low as possible, various proposals for connection are given, as shown in Figure 3. Version A is not particularly advantageous. Here, thin traces are used between the vias and the bypass capacitor. Depending on where on the other side of the board the paths to be supported run, the geometrical arrangement can also lead to increased parasitic inductance. In version B, the vias are brought much closer to the bypass capacitor, thus this is a much better connection. Also, two vias are used in parallel. This reduces the total inductance of the connection. Version C is a very good connection in which the loop area for the connection can be very small, thus there is only a very small amount of parasitic inductance here. However, with very small bypass capacitors and low cost manufacturing processes, vias underneath components are not possible or permissible. Example D can be an interesting connection. Depending on how a specific ceramic bypass capacitor is designed, lateral connection to the board can represent the path with the lowest parasitic inductance. Conclusion Placement of bypass capacitors on the board is very important for achieving the greatest possible effectiveness for these components. Here, connection with as little parasitic inductance as possible is important. The most suitable connection uses the same side of the board as the circuit being supported is on, as shown in Figure 2. In exceptional cases in which connection of the bypass capacitor on the back of the board is necessary, a connection with as little parasitic inductance as possible, as shown in examples B, C, and D in Figure 3, should be selected. Figure 3. When bypass capacitors are connected with vias, there are various options VISIT US AT PCIM BOOTH #9-434 Kool Mµ ® Hƒ Powder Cores Lowest Losses for High Frequencies Optimized for 200-500 kHz Edge ™ Powder Cores Best DC Bias for Cutting Edge Performance and Compact Design www.mag-inc.com DC Bias (Oe) % Initial Permeability µ i 100% 90% 80% 70% 60% 50% 40% 10 100 150 60µ Edge 60µ High Flux Flux Density (Tesla) Core Loss (mW/cm 3 ) 1000 100 20 0.01 0.1 0.2 500 kHz 60µ Kool Mµ 100 kHz 60µ Kool Mµ 500 kHz 60µ Kool Mµ Hƒ 100 kHz 60µ Kool Mµ Hƒ