Power Electronics Europe Issue 4 - November 2022

14 AUTOMOTIVE POWER www.epc-co.com Issue 4 2022 Power Electronics Europe www.power-mag.com balancing and minimizing other effects from mismatch, such as gate drive delay, switching transition speed, overshoot, etc. Figure 2 shows the layout example around the GaN FETs in this design, which utilizes the internal vertical layout technique [3] by placing the decoupling capacitors close the FETs with a solid ground plane underneath. Digital control A dsPIC33CK256MP503 [5] digital controller from Microchip is used in this design. It is a 16-bit processor with a maximum CPU speed of 100 MIPS. The pulse- width modulation (PWM) module can be configured in high-resolution mode, resulting in 250 ps resolution in duty cycle and dead times, allowing accurate adjustment of dead times to fully exploit the high performance of GaN FETs. Digital average current mode control is implemented for both buck and boost modes. The current sensing circuitry consists of sense resistors and differential amplifiers. In this design, low loss 0.2 m sense resistors and low-noise amplifiers MCP6C02 are used. The control block diagram is shown in Figure 3. The same current reference IREF is used for the two independent current loops. As a result, the current in both inductors will be regulated to the same value. The bandwidth of the two inner current loops are set to 6 kHz, and the outer voltage loop bandwidth is set to 800 Hz. Thermal management At full output power of 2 kW, a heatsink is required for the GaN FETs. A standard commercially available 8th brick heatsink is used. Four metal spacers are installed on the PCB to provide the appropriate clearance for the heatsink mounting. A thermal interface material (TIM) is required between the FETs and heatsink. Usually, the material needs to have a) mechanical compliance due to compression, b) electrical insulation and c) good thermal conductivity. In this design, a TIM with 17.8 W/mK is used. Figure 4 shows the 3D heatsink installation view. Figure 5: Photo image of the EPC9165 converter with the EPC9528 dsPIC33CK controller module attached ABOVE Figure 4: Heatsink installation view, showing the metal spacer, thermal interface material Figure 2: Example layout of the top two layers of the printed circuit board around GaN FETs; (a) top layer consisting of ground (GND), switching node (SW) and input (VIN) nets, and (b) middle layer 1 of solid ground plane LEFT Figure 3: Digital average current mode control diagram